The invention relates to digital frequency synthesis, and more particularly, to a high-resolution, programmable digital frequency divider.
In electronic position-fixing systems such as those having transmitters carried in earth-orbitting satellites, it is necessary for a receiver to determine the magnitude of the Doppler shift component of the signal received from the satellite, including contribution to the Doppler shift from the user's motion. In one such position-fixing system, the carrier signals are modulated with pseudo-random noise codes. The codes facilitate satellite identification (each satellite having a unique code), and measurement of the signal propagation time from satellite to user. The receiver synchronizes with the code of a particular satellite by generating within the receiver the code for the satellite, and then correlating the locally generated code with the received signal. After synchronization, both the phase of the carrier signal and the code sequence timing are continuously tracked. One such pseudo-random noise code utilized in the Navstar-Global Positioning System (GPS) is termed a P (Precision) code. The P code operates at 10.23 megabits per second and has a complete cycle of 267 days, each satellite generating an exclusive 7-day long segment of the code. Accordingly, the code generator in the receiver must be capable of extremely fine resolution in order to maintain track and synchronization of the code sequence timing in an environment where the Doppler shift of a 10.23 Mhz signal due to the user's vehicle motion may range from only a few Hertz to several hundred Hertz.
In accordance with the present invention, a first adder/accumulator circuit operating at the code clock frequency controls a dual modulus divider circuit to divide an input digital pulse signal by a fractional quantity to generate a nominal 10.23 MHz code clock. A binary signal representative of the desired Doppler shift is iteratively added it itself in a binary adder/accumulator circuit until a positive or negative overflow signal is generated. The overflow signal, coupled to the first adder/accumulator circuit, controls that circuit to alter the division ratio of the dual modulus divider circuit, thereby altering the code clock frequency by the desired amount.